1. Field of the Invention
The present invention relates to a memory cell, and in particular, to a memory cell including a variable resistor element and a transistor element, a semiconductor memory device provided with an array of memory cells, and a method of manufacturing the same.
2. Description of the Related Art
A variety of device arrangements including FeRAM (ferroelectric RAM), MRAM (magnetic RAM), and OUM (ovonic unified memory) have been contrived as a next-generation nonvolatile random access memory (NVRAM) operable at high speed to take a place of flash memories, and there is a massive development race with respect to higher performance, higher operational reliability, lower manufacturing cost, and process matching. However, each of these memory devices that have been developed so far has its advantages and disadvantages, and realization of the ideal of a universal memory with advantages of all these SRAM, DRAM, and flash memories still remain distant.
In contrast to the prior arts, Shangquing Liu, Alex Ignatiev, and others from University of Houston, USA discloses a method of applying voltage pulses to a perovskite material, which has a super magneto-resistance effect, to reversibly modify the electrical resistance (for example, as disclosed in U.S. Pat. No. 6,204,139 and Lui, S. Q., et al. “Electric-pulse-induced reversible resistance change effect in magneto-resistive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, 2000). This is a major breakthrough where a resistance change can be created in perovskite material known for the super magneto-resistance effect on the order of several digits in room temperature without application of a magnetic field.
FIG. 38 illustrates an exemplary arrangement of a memory array employing the above described advantage. This memory array is arranged where the electrode at each bit is connected with a wire line. In a writing action, pulses for writing data are applied through the wire line. For reading out the data, a current is drawn out from the wire lime.
However, because the semiconductor memory disclosed in the above U.S. Pat. No. 6,204,139 has the electrode at each bit connected with the wire line, it is difficult to increase the degree of circuitry integration as a memory while it is possible to evaluate characteristics of thin film material. In addition, as the semiconductor memory permits writing, reading, and resetting actions to be controlled by an input signal received from the outside, it fails to carry out the writing, reading, and resetting actions without the help of the external signal unlike another conventional semiconductor memory.
In addition to the semiconductor memory shown in FIG. 38, a resistive nonvolatile memory RRAM (resistance random access memory) is known using variable resistor elements with the above described advantage. Such an RRAM, unlike the MRAM, requires no magnetic fields and is low in the power consumption and relatively easy in the miniaturization and the circuitry integration. Also, since the RRAM is significantly wider in the dynamic range of the change of resistance than the MRAM, it may be implemented for multi-level storage. Moreover, its device structure is advantageously simple where a lower electrode material, a perovskite-type oxide, and an upper electrode material are deposited in layers in this order along the vertical to a substrate. In the specification of U.S. Pat. No. 6,204,139, the lower electrode material is a layer of yttrium barium copper oxide, YBa2Cu3O7 (YBCO), deposited on a mono-crystalline substrate of lanthanum aluminum oxide, LaAlO3 (LAO). The perovskite-type oxide is a layer of crystalline praseodymium calcium manganese oxide, Pr1-xCaxMnO3 (PCMO), while the upper electrode material is a layer of Ag deposited by sputtering. The action of the memory element has been reported in which its resistance can reversibly be changed by a pulse voltage of 51 volts applying at positive and negative levels to between the upper and lower electrodes. It is hence proved that a novel nonvolatile memory device is provided where the resistance can be measured during the action of reversibly changing the resistance (referred to as switching action hereinafter).
The applicants of the present invention have found from experiments of the foregoing aspect that a unique characteristic is obtained by applying a CMR featured PCMO (Pr0.7Ca0.3MnO3) which is identical in the perovskite structure to the variable resistor body disclosed in U.S. Pat. No. 6,204,139, with one or more short electric pulses. More specifically, the resistance of the thin film material can be varied from several hundreds Ω to about one million Ω when voltage pulses of substantially ±5 V are applied.
FIG. 39 is a circuitry diagram showing an arrangement of a conventional memory array. A memory array 10 is constituted from a 4×4 matrix of variable resistor elements Rc made from a PCMO material. Each variable resistor element Rc is connected at one end to word lines W1 to W4 and at the other end to bit lines B1 to B4. A periphery circuit 32 is provided adjacent to the memory array 10. Each of the bit lines B1 to B4 is connected with a bit-path transistor 34 thus to form a path to an inverter 38. A load transistor 36 is connected between the bit-path transistor 34 and the inverter 38. Accordingly, the variable resistor elements Rc in the memory array 10 can be operated for the writing and reading of data.
In the conventional memory array, each memory element can be driven at a lower voltage. However, the disadvantage is that a passage of current leakage is developed between the memory cell to be accessed and a memory cell adjacent to the accessed memory cell during the reading action. Accordingly, this may interrupt the evaluation of current during the reading action (read disturb). Also, the current leakage to any adjacent memory cell may disturb the writing action (write disturb).
For example, in the reading action for reading the resistance from a variable resistor element Rca in a target or selected memory cell, the word line W3 is applied with a source voltage Vcc, the bit line B2 remains connected to the ground GND, and the other bit lines B1, B3, B4 and the word lines W1, W2, and W4 stay open. When the bit-path transistor 34a is switched on, a current path denoted by the arrow A1 conducts for reading the resistance. However, since the variable resistor element Rca may simultaneously develop current paths, denoted by the arrows A2 and A3, to an adjacent variable resistor element Rc, its resistance can be read out with much difficulty (the read disturb).
Moreover, in case that the external resistance across a current path connected to the variable resistor element remains not uniform, the application of voltage to the variable resistor element may fail to stay at desired levels. As the result, the writing action will be disturbed or the reading action will suffer from shortage of the current due to the inuniformity of the external resistance.